Embodiments of the present invention relate to a semiconductor processing for the manufacture of semiconductor devices. More particularly, embodiments of the present invention provide a method and device for generating suppress bars and selective optical proximity correction for the manufacture of integrated circuits.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Some semiconductor devices are now being fabricated with features less than 70 nanometers across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility.
Making devices smaller is very challenging, as each process used in IC fabrication has a limit. Various process limitations have made IC fabrication more difficult as the devices get smaller. One area of fabrication technology in which such limitations have appeared is photolithography.
Photolithography involves selectively exposing regions of a resist coated silicon wafer to an illumination pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers.
An integral component of photolithographic apparatus is a “reticle” which includes a pattern corresponding to features at one layer in an IC design. The reticle typically includes a transparent glass plate covered with a patterned light blocking material (e.g., a mask) such as chromium. The reticle is placed between an illumination source producing light of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper is a photoresist-covered silicon wafer. When light from the illumination source is directed onto the reticle, it passes through the glass plate (regions not having chromium patterns) and projects an image onto the photoresist covered silicon wafer. As the exposure wavelength of modern micro lithographic tools continue to decrease, chemically amplified photoresists are becoming more important. Chemical amplification serves to increase the sensitivity of photoresists by creating a photo-generated catalyst (typically an acid) during the exposure. The photoresist is typically baked to undergo chemical changes that alter its dissolution properties. Subsequent development process (e.g., removing the photoresist using etching and/or rinsing) is needed to obtain the projected image on wafer. In this manner, an image of the reticle is transferred to the photoresist.
As light passes through the reticle, it is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. Furthermore, resist processing effects during the bake process, such as nonlinear diffusion of the photo-generated acid, exacerbate the pattern distortion on the wafer. Subsequent pattern transfer processing effects, such as etch bias, further degrade the pattern fidelity. While such effects pose relatively little problem in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they cannot be ignored in layouts having feature sizes smaller than about 1 micron. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process. Recently some semiconductor devices have scaled down to 60 nm.
To remedy this problem, a reticle correction technique known as Optical Proximity Corrections (OPC) has been developed. Optical Proximity Correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass. In addition to the OPC techniques, resolution enhancement technique (RET) is also used to improve quality of reticle patterns. Sometimes, RET is referred to as a type of OPC. In the following sections, resist and photoresist are used interchangeably; mask, photomask, and reticle are used interchangeably; and mask pattern and reticle pattern are used interchangeably.